TsnTec 78M0048 Series_Financial ultra low latency chip_Chip_Products

Products

Chip
Device

System Description

The TsnTec 78M0048 FCE chip utilizes the latest generation of cross serdes design architecture from TesnTec to provide link switching at the physical layer. This chapter presents a system overview, a logical view of the chip, and a module diagram.

The chip supports up to 49 serdes signal inputs.
The chip supports up to 49 serdes signal outputs.
Each input and output can be freely configured for link switching.
Support serdes rate range: 1.25Gbps-12.3125Gbps.
Supports 49 independent CTLE adjustments.
Support programmable output pre-emphasis.
Support 49 independent LOS detection.
Maximum insertion loss: -10dB.
Maximum supported return loss: -8dB.
Low Latency Switch Applications.